Power efficiency for processor-based equipment is becoming increasingly important as people are becoming more attuned to energy conservation issues. Specific considerations are the reduction of thermal effects and operating costs. Also, apart from energy conservation, power efficiency is a concern for battery-operated processor-based equipment, where it is desired to minimize battery size so that the equipment can be made small and lightweight. The "processor-based equipment" can be either equipment designed especially for general computing or equipment having an embedded processor.
For the standpoint of processor design, a number of techniques have been used to reduce power usage. These techniques can be grouped as two basic strategies. First, the processor's circuitry can be designed to use less power. Second, the processor can be designed in a manner that permits power usage to be managed.
In the past, power management has been primarily at the system level. Various "power down" modes have been implemented, which permit parts of the system, such as a disk drive, display, or the processor itself to be intermittently powered down.
The entry of a device into a power down mode can be initiated in various ways, such as in response to a timer or in response to an instruction from the processor. In the case of the former, the timer automatically shifts the device into a power down mode after it has been inactive for a preset period. In the case of the latter, i.e., instruction-implemented power management, various standards have been developed to place power management under processor control. One such standard is the Advanced Power Management interface specification, developed jointly by Intel and Microsoft.
One approach to processor power management is described in U.S. Pat. No. 5,584,031, entitled "System and Method for Executing a Low Power Delay Instruction". A special instruction (a "sleep" opcode) specifies a number of timing cycles during which activity of the central processing unit is delayed.
Another approach to processor power management is described in U.S. Pat. No. 5,495,617, entitled "On Demand Powering of Necessary Portions of Execution Unit by Decoding Instruction Word Field Indications Which Unit is Required for Execution". An instruction decoder differentiates "control" instructions from "execute" instructions. If the instruction is a "control" instruction, it does not involve the execution unit, and a standby signal can be sent to the execution unit.